1. Field of the Invention
This invention relates to magnetic memory devices and, more particularly, to a circuit and method for providing tunable writing current magnitudes to the magnetic memory devices within a magnetic memory circuit.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Recently, advancements in the use of magneto-resistive materials have progressed the development of magnetic random access memory (MRAM) devices to function as viable non-volatile memory circuits. In general, MRAM devices exploit the electromagnetic properties of magneto-resistive materials to set and maintain information stored within the individual memory cells of the circuit. In particular, MRAM circuits utilize magnetic direction to store information within a memory cell, and differential resistance measurements to read information from the memory cell. More specifically, information is stored within an MRAM cell as a magnetic bit, the state of which is indicated by the magnetic moment direction within one layer of the memory cell relative to another layer of the memory cell. For example, information may be stored within an upper layer as either a parallel or antiparallel magnetic moment direction relative to a magnetic moment direction of a lower magnetic layer. Note that the term antiparallel is used herein to describe a magnetic moment direction oriented 180xc2x0 from the magnetic moment direction of the lower magnetic layer. In addition, a differential resistance can be measured between layers of the memory cell. Such a differential resistance indicates a difference in the magnetic moment directions between layers of the memory cell, and thus, can be used to read the magnetic state of the bit stored within the memory cell.
In order for a magnetic element to operate as a memory cell, it must be adapted to maintain two substantially different resistance states (i.e., representing two different magnetic states). It may be preferred, however, that a magnetic memory cell be adapted to maintain two substantially different resistance states at rest (i.e., when substantially no external magnetic field is applied to the cell). Such a magnetic memory cell may need substantially less operating current than a memory cell not adapted to maintain different magnetic states at rest.
More specifically, it is desirable that a magnetic memory cell is adapted to maintain either a parallel or an antiparallel magnetic state at rest. Such a case may be equivalent to having a nearly centered resistance (R) versus magnetic field (or, applied current, I) response, such as the R-I curve illustrated in FIG. 2A. In other words, optimum MRAM operation usually exhibits a nearly centered resistance versus applied current response, and thus, allows substantially equal thresholds of writing current to switch the magnetic state of the memory cell from a low resistance state to a high resistance state, and vice versa. As such, FIG. 2A depicts an ideal response in which the magnitude of current (|I1|) needed to switch the magnetization from a low to high resistance state is substantially equal to the magnitude of current (|I2|) needed to switch the magnetization from a high to low resistance state. In addition, a magnetic memory cell demonstrating a nearly centered R-I curve can maintain two substantially different magnetic states (reference numerals 32a and 32b) at rest.
However, the R-I curve may be significantly affected by variations within and/or between individual memory cells of an MRAM circuit. As such, it is not typical that all memory cells within the MRAM circuit exhibit such a nearly centered R-I curve. Instead, a portion of the memory cells within the circuit may demonstrate an offset in the R-I curve. In some cases, the offset may be such that two substantially different magnetic states can be maintained at rest. Such an offset, however, may introduce unequal thresholds of writing current between the two magnetic states, thereby requiring substantially more current to switch one magnetic state versus the other. In other cases, however, the offset may be such that only one magnetic state can be maintained at rest. An offset of such a degree typically results in false write operations, thereby indicating failure of the memory device to store accurate information.
In some cases, the R-I curve may be significantly affected by variations within individual memory cells that cause ferromagnetic coupling between layers of the cells. During fabrication of MRAM cells, for example, individual cell layers may be fabricated having surfaces that are not completely flat but instead exhibit surface and/or interface roughness. Such variation in surface topology causes the formation of magnetic poles along an interface between two or more layers of the MRAM cell. In this manner, interface roughness causes unintentional magnetic coupling of the magnetic poles formed along the interface. Such unintentional magnetic coupling tends to introduce an offset into the R-I curve by forcing the magnetic moments of the two or more cell layers to point along a single direction. Therefore, such unintentional magnetic coupling may be referred to as ferromagnetic or positive coupling. Note, however, that ferromagnetic coupling typically produces an offset in the same direction as the direction of current (I) flow along the width of the memory cell that causes a high resistance state in the memory cell. For example, ferromagnetic coupling may introduce a positive offset into the R-I curve if the direction of current flow along the width of the memory cell is in a positive direction.
In other cases, an offset may be introduced into the R-I curve on account of antiferromagnetic coupling. Antiferromagnetic coupling generally refers to the unintentional magnetic coupling between an upper magnetic layer, which stores memory information, and the ends of one or more lower magnetic layers, which have magnetic moments fixed in a particular direction. As such, an offset may be introduced into the R-I curve when the combined magnetic moments of the one or more lower magnetic layers are non-zero. In this case, such unintentional magnetic coupling introduces an offset into the R-I curve by forcing the magnetic moments of the upper and lower magnetic layers to point along substantially opposite directions. This offset, termed negative offset, is generally along the same direction as the direction of current (I) flow along the width of a memory cell that causes a low resistance state in the memory cell. Thus, such unintentional magnetic coupling is generally referred to as antiferromagnetic or negative coupling.
Any offset (positive or negative), however, may produce unequal thresholds of writing current, such that substantially more current is needed to write one magnetic state versus another magnetic state within an individual memory cell. Such unequal thresholds of writing current may cause a false write operation to occur in one or more memory cells of the MRAM circuit, thereby causing the memory device to store inaccurate information.
As stated above, it is desirable for a magnetic memory cell to maintain two substantially different magnetic states at rest. In some embodiments, however, unintentional ferromagnetic coupling may introduce a positive offset so severe that only one magnetic state, such as the low resistance state, can be maintained when no external magnetic field is applied. In FIG. 2B, for example, the positive offset introduced into the R-I curve may be so large that only a low resistance state (reference numeral 34) is maintained when no external magnetic field is applied (i.e., when the applied current, I, is substantially zero). In such a case, a biasing magnetic field (and thus, a biasing current) may be needed to maintain a high resistance state in the presence of unintentional ferromagnetic magnetic coupling.
In other embodiments, unintentional antiferromagnetic coupling may introduce a negative offset so severe that only one magnetic state, such as a high resistance state, can be maintained when no external magnetic field is applied. In FIG. 2C, for example, the negative offset introduced into the R-I curve may be so large that only a high resistance state (reference numeral 36) is maintained when no external magnetic field is applied. In such a case, a biasing magnetic field (and thus, a biasing current) may be needed to maintain a low resistance state in the presence of unintentional antiferromagnetic magnetic coupling.
In either embodiment of FIG. 2B or 2C, ferromagnetic and/or antiferromagnetic coupling generally causes failure of the MRAM circuit without the application of a biasing magnetic field. Such failure is typically due to the inability of one or more memory cells to maintain two substantially different magnetic states at rest. The application of such a biasing magnetic field, however, generally causes an undesirable increase in the power consumed by the MRAM circuit.
Therefore, it would be advantageous to develop a magnetic memory circuit that overcomes the problems described above. In general, it would be advantageous to provide a magnetic memory circuit, which is unaffected by unintentional magnetic coupling, such as ferromagnetic and antiferromagnetic coupling. In particular, it would be advantageous to provide a magnetic memory circuit and method of construction that substantially eliminates the occurrence of false write operations within individual cells of the magnetic memory circuit. In this manner, the amount of power consumed by a memory circuit may be reduced, as compared to a memory circuit that does not compensate for unintentional magnetic coupling.
The problems outlined above may be in large part addressed by a circuit adapted to supply different current magnitudes along opposing directions of a conductive line. Such a circuit may be particularly beneficial in compensating for the effects of unintentional magnetic coupling, such as ferromagnetic and antiferromagnetic coupling, within MRAM devices. In addition, a method is provided herein which determines tunable write current magnitudes for conductive lines arranged within a circuit. In one example, the tunable writing currents advantageously increase the current margin between select and disturb cells (i.e., increase the write selectivity), to thereby decrease the probability of storing inaccurate information within the memory circuit. More specifically, the tunable writing currents may compensate for ferromagnetic and antiferromagnetic coupling within magnetic memory cells caused by uneven surface topology and non-zero total magnetic moments of the fixed magnetic layers, respectively. In addition, the tunable writing currents may compensate for variations in cell fabrication processes, such as overlay variations produced in the masking and etching processes.
As stated above, a circuit is provided which is adapted to supply current at a first magnitude along one direction of a conductive line arranged within the circuit. In addition, the circuit is adapted to supply current at a second magnitude along an opposite direction of the conductive line. In some embodiments, the circuit may also supply the first and second current magnitudes to a plurality of other conductive lines aligned with the conductive line. In some cases, the conductive line is a bit line, such that current may be supplied along a direction and an opposite direction of the bit line. In other cases, however, the conductive line is a digit line, such that current may be supplied along one direction and an opposite direction of the digit line. In any case, the first and second current magnitudes may be substantially different. Such a difference may advantageously compensate for a non-centered resistance versus current response, which may be produced by unintentional magnetic coupling within individual memory cells of the circuit. As such, the circuit provided herein may demonstrate an increased selectivity for write operations in memory cells, which exhibit non-centered resistance versus current responses.
In some cases, the circuit provided herein may exhibit a write selectivity having a current margin equal to or greater than approximately 0.8 mA. In particular, the circuit may exhibit a write selectivity having a current margin between about 0.8 mA and about 2.5 mA. The current margin, as described herein, is the difference between a minimum current value needed to switch a disturbed memory cell and a maximum current value needed to switch a selected memory cell. The maximum current value may be described as the amount of current supplied to one or more parallel conductive lines, which induces a magnetic field strong enough to switch the magnetic direction of substantially all selected memory cells arranged along the one or more parallel conductive lines. Alternatively, the minimum current value may be described as the amount of current supplied to one or more parallel conductive lines, which induces a magnetic field strong enough to switch the magnetic direction of at least one disturbed memory cell arranged along the one or more parallel conductive lines.
In addition, the circuit provided herein may include at least one magnetic memory cell. Such a magnetic memory cell may be adapted to maintain a first magnetic direction within a first magnetic layer of the memory cell. In some cases, the first magnetic layer may be referred to as a pinned magnetic layer, such that the magnetic moment or magnetization of the layer is xe2x80x9cpinnedxe2x80x9d in a predefined or reference direction. Furthermore, the magnetic memory cell of the circuit may be adapted to maintain a second magnetic direction within a second magnetic layer of the memory cell. In such an embodiment, the second magnetic layer may be referred to as a fixed magnetic layer, such that the magnetization of the layer is xe2x80x9cfixedxe2x80x9d in a second magnetic direction, which is opposite to the first magnetic direction. Moreover, the magnetic memory cell of the circuit may be adapted to alter a third magnetic direction within a third magnetic layer of the magnetic memory cell. Such a third magnetic layer may be referred to as a free or soft magnetic layer, in some embodiments, such that the magnetization of the layer is xe2x80x9cfreexe2x80x9d to switch between same and opposite magnetic directions relative to the reference magnetic direction of the first magnetic layer.
Furthermore, the magnetic memory cell may include a relatively thin, nonmagnetic coupling layer, which may separate the first and second magnetic layers of a magnetic memory cell to create a synthetic antiferromagnetic stack (xe2x80x9cSAFxe2x80x9d). In this manner, the SAF is referred to as xe2x80x9cbalancedxe2x80x9d when the first and second magnetic layers include substantially similar thicknesses. Alternatively, the SAF is xe2x80x9cunbalancedxe2x80x9d when the first and second magnetic layers include substantially different thicknesses. As such, the circuit provided herein may exhibit increased write selectivity for magnetic memory cells having balanced or unbalanced SAF stacks.
Moreover, the magnetic memory cell may include an upper portion and a lower portion, such that the upper portion demonstrates a narrower width than the lower portion. In some cases, the upper portion includes the third and second magnetic layers while the lower portion includes the first magnetic layer. In other cases, however, it may be desired that the upper portion includes the third magnetic layer while the lower portion includes the first and second magnetic layers. In such a case, the third magnetic layer exhibits a narrower width than the widths of the first and second magnetic layers. In this manner, decreasing the width of the third magnetic layer tends to reduce the occurrence of electrical shorting across a spacer layer (i.e., tunnel barrier layer) arranged between the third magnetic layer and the second magnetic layer. The third magnetic layer, however, is typically patterned during a separate processing step than the patterning process of the lower portion. As such, variations in the separate processing step may cause the third magnetic layer to be formed overlying the lower portion in a position, which may vary from cell to cell (i.e., overlay variation). As will be described in more detail below, the circuit may compensate for such overlay variations by supplying writing currents having variable magnitudes (i.e., tunable writing currents).
In another embodiment, a method is provided herein for configuring a device having a magnetic memory array, such as the circuit described above. The method includes configuring the device to receive a first current magnitude along one direction of the magnetic memory array. In some cases, the method further includes configuring the device to receive a second current magnitude along an opposite direction of the magnetic memory array, such that the second current magnitude is substantially different from the first current magnitude. In other cases, however, the method may include configuring the device to receive a second current magnitude, which is substantially equal to the first current magnitude, along the opposite direction of the magnetic memory array. In any case, the first and second current magnitudes include write operation current magnitudes for the magnetic memory array. As such, the method may include configuring the device to receive the first and second current magnitudes along a bit line or, alternatively, along a digit line of the device. Alternatively, the method may include configuring the device to receive the first and second current magnitudes along both a bit line and a digit line of the device. Therefore, the method provides tunable writing currents along either the bit line, the digit line, or along both the bit line and the digit line.
In yet another embodiment, a method is provided herein for assigning tunable write operation current magnitudes to memory cells within a magnetic memory array. In particular, the method includes determining a first write operation current magnitude along a direction of a conductive line arranged within the magnetic memory array. In addition, the method includes separately determining a second write operation current magnitude along an opposite direction of the conductive line. In one example, the first write operation current magnitude may be adapted to switch the magnetic state of a selected memory cell from a parallel to an antiparallel state. As such, the second write operation current magnitude may be adapted to switch the magnetic state of the selected memory cell from an antiparallel to a parallel state. Alternatively, the first write operation current magnitude may be adapted to switch the magnetic state from an antiparallel to a parallel state, whereas the second write operation current magnitude may be adapted to switch the magnetic state from a parallel to an antiparallel state. In some cases, the steps of determining the first and second write operation current magnitudes are conducted consecutively. In other cases, however, the steps of determining the first and second write operation current magnitudes are conducted simultaneously.
In any case, the step of determining the first write operation current magnitude may include applying current along the one direction of the conductive line to determine a first current margin between a write operation current magnitude of a disturbed memory cell and a write operation current magnitude of a selected memory cell. Subsequently, the method may include designating a first current magnitude within the first current margin to be applied along the one direction of the conductive line. In addition, the step of separately determining the second write operation current magnitude may include applying current along the opposite direction of the conductive line to determine a second current margin between a write operation current magnitude of a disturbed memory cell and a write operation current magnitude of a selected memory cell. Subsequently, the method may include designating a second current magnitude within the second current margin to be applied along the opposite direction of the conductive line. As stated above, the first write operation current magnitude may be different than the second write operation current magnitude, in some cases. In other cases, however, the first write operation current magnitude may be substantially equal to the second write operation current magnitude.